Composite gate dielectric layer

ABSTRACT

A semiconductor device having composite dielectric layer formed between a silicon substrate and a gate electrode. The composite gate dielectric layer including a layer of silicon oxide, SiO X≦2 , having a dielectric constant of greater than about 3.9 and about 12 or less, and a complementary dielectric layer for inhibiting the flow of leakage current through the composite dielectric layer.

FIELD OF THE INVENTION

[0001] The present invention relates to semiconductor devices.

BACKGROUND OF THE INVENTION

[0002] In a field effect transistor (“FET”), a capacitance is associatedwith a gate dielectric layer, which insulates a gate electrode from achannel disposed within a semiconductor substrate. As semiconductordevices continue to be scaled down to reduce power consumption, thedemand for higher input FET capacitances has increased. The inputcapacitance of a FET may be increased by either reducing the thicknessof the gate dielectric layer or increasing its dielectric constant.

[0003] Gate dielectric layers have historically been realized by bulksilicon dioxide, SiO₂. To date, industry has been reducing the thicknessof bulk silicon dioxide-based gate dielectric layers to increase inputFET capacitances. However, at thicknesses of less than about 15 Å, bulksilicon dioxide becomes exceedingly susceptible to leakage currentstunneling through the gate dielectric layer. Thus, the leakage currentproblem is now becoming a practical concern.

[0004] To overcome this leakage current problem, industry has begun toexplore various alternatives materials. These alternative materials havea dielectric constant greater than that of bulk silicon dioxide. Asinput FET capacitance is directly proportional to the dielectricconstant of the gate dielectric layer and inversely proportional to thegate dielectric layer's thickness, it is believed that one of thesealternative materials may enable the formation of a gate dielectriclayer of a sufficient thickness to ameliorate the leakage currentproblem, while also increasing the input FET capacitance. Typicalmaterials being investigated include metal-silicon-oxynitride and metalsilicate, for example.

[0005] The use of such alternative materials as gate dielectric layersgives rise to other problems, however. The interface between thealternative materials under consideration and the underlying siliconsubstrate is of a poorer quality than the interface between bulk silicondioxide and the silicon substrate. This poorer interface quality,attributable to several factors including an increased number of defects(e.g., dangling bonds) at the silicon interface, as well as the numbersof charges to become trapped by these defects. The trapped chargesdegrade device performance, reduce the reliability of the gatedielectric layer, and, therefore, reduce the FETs' so-called “mean timebetween failure.”

[0006] In accordance with the invention of our co-pending, commonlyassigned, U.S. patent application, entitled “A SILICON OXIDE BASED GATEDIELECTRIC LAYER,” Ser. No. ______, filed concurrently with the presentapplication, we have recognized that the search for gate dielectricmaterials other than silicon dioxide is somewhat misplaced. Theinvention in our co-pending application takes advantage of the silicondioxide/silicon interface study, as reported by two of us in “TheElectronic Structure at the Atomic Scale Of Ultrathin Gate Oxides,”Nature, Vol. 399, June 1999, which theorizes that a layer of siliconoxide (SiO_(X≦2)) of a sufficient thickness may exhibit a dielectricconstant greater than that of bulk silicon dioxide (i.e., about 3.9). Inthe aforementioned co-pending patent application, a gate dielectriclayer may be advantageously formed from at least one layer of thesilicon oxide (SiO_(X≦2)) to increase the input FET capacitance, whilealso providing a desirable interface with a silicon substrate.

SUMMARY OF THE INVENTION

[0007] We have recognized that a gate dielectric layer formed of atleast one layer of silicon oxide (SiO_(X≦2)) having a thickness of about5 Å or less may be insufficient to withstand leakage current problems.Consequently, we have invented a composite gate dielectric layer havinga complementary dielectric layer formed upon a layer of silicon oxide(SiO_(X≦2)). The complementary dielectric layer is of sufficientthickness to substantially inhibit the flow of leakage current.

[0008] The addition of the complementary dielectric layer will likelyreduce the input FET capacitance. As such, the complementary dielectriclayer has a dielectric constant greater than that of the layer ofsilicon oxide. For example, the complementary dielectric layer may beformed from at least one of aluminate, silicate, ZrO₂, HfO₂, TiO₂,Gd₂O₃, Y₂O₃, Si₃N₄, Ta₂O₅ and Al₂O₃. By judiciously choosing analternative material for the complementary dielectric layer, and anappropriate thickness, a gate dielectric layer may be provided whichexhibits an advantageous combination of properties (i.e., increasedcapacitance and reduced leakage current, for example) not achieved bythe prior art approaches of fabricating a gate dielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present invention will be better understood from reading thefollowing description of non-limiting embodiments, with reference to theattached drawings, wherein below:

[0010]FIG. 1 is a graphical illustration of an embodiment of the presentinvention;

[0011]FIG. 2 is a cross-sectional view of an embodiment of the presentinvention;

[0012]FIG. 3 is a cross-sectional view of another embodiment of thepresent invention; and

[0013]FIG. 4 is a flow chart of another embodiment of the presentinvention.

[0014] It should be emphasized that the drawings of the instantapplication are not to scale but are merely schematic representations,and thus are not intended to portray the specific dimensions of theinvention, which may be determined by skilled artisans throughexamination of the disclosure herein.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0015] As stated hereinabove, the input capacitance of a field effecttransistor (“FET”) is associated with a gate dielectric layer positionedbetween a gate electrode and a channel disposed within a siliconsemiconductor. The continued pursuit of increasing input FETcapacitances has led industry to two alternatives—namely, reducing thethickness of the gate dielectric layer, or increasing the dielectricconstant of the gate dielectric layer. These efforts are driven by theinverse relationship between capacitance and the thickness of the gatedielectric layer, as well as the direct relationship between capacitanceand dielectric constant. These relationships may be expressed using thefollowing mathematical equations:

C=[ε ₀ _(^(*)) k _(^(*)) A]/t

[0016] or

C/A=[ε ₀ _(^(*)) k]/t

[0017] where C is the capacitance, A is the area (length by width) ofthe dielectric layer, C/A is the capacitance per unit area, ε₀ is aconstant (i.e., 8.854×10⁻¹² Farads/meter) referred to as thepermittivity in free space, k is the dielectric constant of thedielectric layer, and t is the thickness of the dielectric layer. Fromthese mathematical expressions, it can be seen that the capacitance perunit area, C/A, may be increased by either decreasing the thickness, t,or increasing the dielectric constant, k.

[0018] Various advantages have been recognized in employing bulk silicondioxide, SiO₂, as a gate dielectric layer at the interface of a silicon(Si) substrate. Consequently, efforts have been expended to fabricategate dielectric layers from continuously thinner layers of bulk silicondioxide, SiO₂. This drive to produce thinner bulk silicon dioxide layersis a result of its fixed dielectric constant, k.

[0019] Referring to FIG. 1, the characteristics of a layer of siliconoxide, SiO_(X≦2), according to an embodiment of the present inventionare graphically illustrated. For the purposes of the present invention,silicon oxide, SiO_(X≦2), is an oxide-based compound having astoichiometry in which each silicon atom is bonded with four or lessoxygen atoms. We have observed that at certain atomic thicknesses,silicon oxide, SiO_(X≦2), exhibits a dielectric constant greater thanthat of bulk silicon dioxide. This general observation was initiallytheorized in the aforementioned study reported by two of us in “TheElectronic Structure at the Atomic Scale Of Ultrathin Gate Oxides,”Nature, Vol. 399, June 1999. Given its material composition, the layerof silicon oxide, SiO_(X≦2), creates a high quality interface withsilicon. Consequently, we have recognized that a layer of silicon oxide,SiO_(X≦2), may be advantageously employed as a gate dielectric layer toincrease the input capacitance per unit area of a semiconductor device,such as a field effect transistor (“FET”).

[0020]FIG. 1 graphically depicts the dielectric constant of a layer ofsilicon oxide, SiO_(X≦2), as a function of the layer's thickness. At athickness of about 5 Å, the dielectric constant of the layer of siliconoxide, SiO_(X≦2), begins to increase beyond that of bulk silicon dioxide(i.e., about 3.9). Our inventive efforts have uncovered that thedielectric constant of the layer of silicon oxide, SiO_(X≦2), peaksbelow 3 Å. We believe that the layer of silicon oxide reaches adielectric constant in the range of about 8 to 12, at a thickness ofabout 3 Å or less. Consequently, we have recognized the advantageousnessof forming a gate dielectric layer employing this layer of siliconoxide, SiO_(X≦2), at the interface with the silicon substrate. Theincreased dielectric constant is a consequence of the proximity of theoxide layer to a material with a smaller bandgap—it is not necessary forthe silicon oxide, SiO_(X≦2), to be substoichiometric in the presentinvention.

[0021] Referring to FIG. 2, a first embodiment of the present inventionis illustrated. Here, a cross-sectional view of a semiconductor device10, such as a metal oxide semiconductor FET (“MOSFET”), for example, isshown. Other devices, however, will be apparent to skilled artisans uponreviewing the instant disclosure.

[0022] Semiconductor device 10 comprises a silicon substrate 20 having aconductive channel 30 electrically connected to a source 40 and a drain50. Above channel 30 is a conductive layer, such as a gate electrode 70.By this arrangement, a gate dielectric layer 60 may be formed betweenchannel 30 and gate electrode 70. As gate dielectric layer 60 hasinsulative properties, an input capacitance is formed between channel 30and gate electrode 70.

[0023] To increase the input capacitance per unit area of device 10, wehave recognized that gate dielectric layer 60 may be formed from a layerof silicon oxide, SiO_(X≦2). The layer of silicon oxide, SiO_(X≦2), asdepicted in FIG. 1, exhibits a dielectric constant, k, greater than thatof bulk silicon dioxide (i.e., about 3.9). As reflected in FIG. 1, thislayer of silicon oxide, SiO_(X≦2), has a thickness of about 5 Å or lessto realize this increased dielectric constant. The dielectric constantof this layer of silicon oxide, SiO_(X≦2), may be optimized in view ofthe potential flow of leakage current through gate dielectric layer 60.

[0024] In an advantageous embodiment, device 10 is operative with thelayer of silicon oxide, SiO_(X≦2), having at a thickness of about 4.5 Åand a dielectric constant of about 8.

[0025] Referring to FIG. 3, a cross-sectional view of a semiconductordevice 100, such as a MOSFET, is illustrated according to a secondembodiment of the present invention. As with semiconductor device 10 ofFIG. 2, device 100 comprises a conductive channel 30 electricallyconnected to a source 40 and a drain 50, each of which are formed withina silicon substrate 20. Above channel 30 is a conductive layer, such asa gate electrode 70.

[0026] Formed between channel 30 and a gate electrode 70, is a gatedielectric layer 65. Gate dielectric layer 65 comprises a first layer 60of silicon oxide, SiO_(X≦2). First layer 60 has a dielectric constant,k, greater than that of bulk silicon dioxide. As shown in FIG. 1, firstlayer 60 has a thickness of about 5 Å or less to realize this increaseddielectric constant.

[0027] To further reduce the propensity of leakage current, gatedielectric layer 65 of device 100 comprises a second layer 80 of siliconoxide, SiO_(X≦2). Second layer 80 may also include one or moreadditional layers of silicon oxide, SiO_(X≦2). Second layer 80, muchlike first layer 60, exhibits a dielectric constant, k, greater thanabout 3.9. To realize this dielectric constant, second layer 80 has athickness of about 5 Å or less.

[0028] It should be noted that the inclusion of second layer 80, inconjunction with first layer 60, reduces the input capacitance per unitarea of device 100 because the positioning of second layer 80 upon firstlayer 60 of silicon oxide, SiO_(X≦2), creates a series capacitance. Assuch, the input capacitance, C_(IN), of device 100 may be expressedusing the following mathematical equations:

1/C _(IN)=1/C ₁+1/C ₂

[0029] or

C _(IN) =[C ₁ _(^(*)) C ₂ ]/[C ₁ +C ₂]

[0030] where C₁ is the capacitance created by first layer 60, and C₂ isthe capacitance created by the second layer 80. Given the mathematicalrelationship between capacitance, dielectric constant and thickness, theabove expressions may be restated as follows:

C _(IN)=[ε₀ _(^(*)) k ₁ _(^(*)) k ₂ _(^(*)) A ₁ _(^(*)) A ₂ ]/[t ₁_(^(*)) k ₂ _(^(*)) A ₂ +t ₂ _(^(*)) k ₁ _(^(*)) A ₁]

[0031] where t₁ and t₂ are the thicknesses of first and second layers,60 and 80, k₁ and k₂ are the dielectric constant of first and secondlayers, 60 and 80, and A₁ and A₂ are the areas of first and secondlayers, 60 and 80. If first and second layers, 60 and 80, have the samewidth and lengths, and thus the same areas (i.e., A₁=A₂), then the abovemathematical expression may be further restated as follows:

C _(IN) /A=[ε ₀ _(^(*)) k ₁ _(^(*)) k ₂ ]/[t ₁ _(^(*)) k ₂ +t ₂ _(^(*))k ₁]

[0032] where C_(IN)/A is input capacitance per unit area. From thehereinabove mathematical equations, input capacitance per unit area willdecrease with the addition of second layer 80. As such, the thickness ofsecond layer 80 may be optimized to further minimize the potential flowof leakage current through gate dielectric layer 65, while providing themaximum possible capacitance per unit area for device 100.

[0033] By this design, it is believed that the inclusion of second layer80 in gate dielectric layer 65 reduces the leakage current over device10 in FIG. 2. Second layer 80 advantageously may have a thickness ofabout 3.5 Å, a dielectric constant of in the range of about 9-10. Theinclusion of second layer 80 also enables the thickness of first layer60 to be potentially reduced to about 3.5 Å such that its dielectricconstant is also in the range of about 9-10.

[0034] Referring to FIG. 4, a third embodiment of the present inventionis illustrated. Here, a cross-sectional view is shown of a semiconductordevice 110. As with devices 10 and 100 of FIGS. 2 and 3, device 110comprises a conductive channel 30 electrically connected to a source 40and a drain 50, each of which are formed within a silicon substrate 20.

[0035] Formed between channel 30 and a gate electrode 70 is a compositedielectric layer 75. Composite dielectric layer 75 comprises at leasttwo dielectric layers, one of which being a layer 60 of silicon oxide,SiO_(X≦2). First layer 60 has a dielectric constant, k, greater thanabout 3.9, and as such, a thickness of about 5 Å or less. First layer 60is formed upon channel 30 to provide an interface with silicon substrate20 which is less rough in comparison with the alternative materialspresently being explored for use as gate dielectric layers.

[0036] To further reduce the propensity of leakage current, compositedielectric layer 75 of device 110 comprises a complementary dielectriclayer 90 formed from alternative materials. Complementary dielectriclayer 90 has a higher dielectric constant than that of layer 60 ofsilicon oxide, SiO_(X≦2). By selecting an alternative material havingsuch a dielectric constant, complementary dielectric layer 90 may besufficiently thicker than second layer 80 of FIG. 3 to further inhibitthe flow of leakage current, all while maintaining the capacitance perunit area of device 110. Consequently, complementary dielectric layer 90may have a thickness as high as about 60 Å, for example. Alternativematerials considered for these purposes include, but are not limited toaluminates, silicates, ZrO₂, HfO₂, TiO₂, Gd₂O₃, Y₂O₃, Si₃N₄, Ta₂O₅ andAl₂O₃. Various substitutes will be apparent to skilled artisans uponreviewing the instant disclosure.

[0037] We estimate that complementary dielectric layer 90 advantageouslymay have a dielectric constant of greater than about 7 and as high asabout 30—though higher dielectric constants may be derived by skilledartisans upon reviewing the instant disclosure—a thickness range ofabout 5 Å and 60 Å. We believe that the inclusion of complementarydielectric layer 90 within composite gate dielectric layer 75 willfurther reduce the leakage current.

[0038] Referring to FIG. 5, a flow chart is illustrated. This flow chartdepicts a number of methods for forming a gate dielectric layer.Variations and substitutions to the recited methods will be apparent toskilled artisans upon reviewing the disclosure herein.

[0039] According to a first processing path along the flow chart, adielectric layer is formed upon a clean silicon substrate. Initially, athermal layer of silicon dioxide is grown upon a clean silicon (Si)substrate. This growth step may be realized by rapid thermal oxidationat a temperature of about 1000° C., for about 5 seconds or less, at apressure of 0.5 mTorr or less. Similar results have been obtained usinga furnace at a temperature of about 800° C. or more, for about 10seconds or more, at a pressure of about one (1) mTorr or less. Atransition metal, such as Zr, Hf or Ti, for example, is subsequentlyimplanted into the thermally grown layer of silicon dioxide. Thereafter,the implanted thermally grown layer of silicon dioxide is annealed in anO₂ atmosphere at a temperature of about 800° C. or more, for about 5seconds or less, at a pressure of about one (1) mTorr or less. Theanneal step forms a layer of silicon oxide, SiO_(X≦2), upon the siliconsubstrate, and the aforementioned complementary dielectric layer uponthe silicon oxide layer. It should be noted that an etch back step mayalso be performed after the growth step, as well as after the implantstep to insure that the resultant thickness of the silicon oxide isabout 5 Å or less. This etch back step may be performed using an HFchemistry, as well as atomic scale electron-energy-loss spectroscopy(“EELS”) to ascertain the appropriate thickness.

[0040] According to a second processing path, a layer of silicon oxide,SiO_(X≦2), is formed upon a clean silicon substrate using atomic layerchemical vapor deposition (“ALCVD”) techniques. Here, a monolayer ofoxygen is first formed upon the substrate by ALCVD. In practice,however, a monolayer of a hydroxyl group is first formed upon thesubstrate by ALCVD. A monolayer of silicon (with a ligand) is thereafterformed upon the monolayer of oxygen (or hydroxyl group), and a secondmonolayer of oxygen (again in practice a hydroxyl group) is formed uponthe monolayer of silicon (with a ligand). Each ALCVD step may beadvantageously performed at a temperature of about 1000° C. Furthermore,each ALCVD step includes the step of introducing an oxygen or siliconprecursor dose of about 10¹⁵ atoms/cm². Once the layer of silicon oxideis formed, the complementary dielectric layer may be formed upon thelayer of silicon oxide. Alternatively, a second layer(s) of siliconoxide may be formed upon the layer of silicon oxide.

[0041] According to a third processing path, a composite dielectriclayer is formed upon a clean silicon substrate by either a metal organicchemical vapor deposition (“MOCVD”) or a low pressure chemical vapordeposition (“LPCVD”) technique. As part of these MOCVD or LPCVD steps,gaseous ZrO and SiO are introduced in the presence of the substrate.Upon performing an anneal step in an O₂ atmosphere at a temperature ofabout 800° C. or more, for about 5 seconds or less, at a pressure ofabout (1) mTorr or less, a layer of silicon oxide, SiO_(X≦2), is formedupon the substrate, and a metal-silicate is formed upon the layer ofsilicon oxide.

[0042] According to a fourth processing path, a composite dielectriclayer is formed by initially evaporating a metal in an O₂ atmosphere.These metal atoms, deposited by any means, such as CVD or PVD, forexample, form a layer of metal-oxide or metal-silicide upon the cleanedsilicon substrate. Thereafter, an anneal step is performed in an O₂atmosphere at a temperature range of about 800° C. and 1100° C., forabout 5 seconds or less, at a pressure of about one (1) mTorr or less.Consequently, a layer of silicon oxide, SiO_(X≦2), is formed upon thesubstrate, and a layer of metal-silicate is formed upon the layer ofsilicon oxide.

[0043] According to a fifth processing path along the flow chart, acomposite dielectric layer is formed by initially sputtering transitionmetal atoms into an O₂ atmosphere having a temperature or about 800° C.or more. As an alternative to sputtering, a chemical vapor deposition oran evaporation step may be performed. These metal atoms form a layer ofmetal or metal-silicide upon the cleaned silicon substrate. Thereafter,an anneal step is performed in an O₂ atmosphere at a temperature ofabout 800° C. ore more, for about 5 seconds or less, at a pressure ofabout one (1) mTorr or less. Consequently, a layer of silicon oxide,SiO_(X≦2), is formed upon the substrate, and a layer of metal-silicateis formed upon the layer of silicon oxide.

[0044] While the particular invention has been described with referenceto illustrative embodiments, this description is not meant to beconstrued in a limiting sense. It is understood that although thepresent invention has been described, various modifications of theillustrative embodiments, as well as additional embodiments of theinvention, will be apparent to one of ordinary skill in the art uponreference to this description without departing from the spirit of theinvention, as recited in the claims appended hereto. Thus, while a gatedielectric layer for a field effect transistor (“FET”) and a method offabricating a gate dielectric layer is disclosed, it should be apparentto skilled artisans that the present invention may be applied todielectric layers generally, as well as other devices requiringincreased capacitance per unit area. It is therefore contemplated thatthe appended claims will cover any such modifications or embodiments asfall within the true scope of the invention.

1. A semiconductor device comprising: a conductive layer; a siliconsubstrate; and a composite gate dielectric layer formed between thesilicon substrate and the conductive layer, the composite gatedielectric layer comprising: a layer of silicon oxide, SiO_(X≦2), havingdielectric constant greater than about 3.9 and about ≦12; and acomplementary dielectric layer disposed upon the layer of silicon oxide.2. The semiconductor device of claim 1, wherein the layer of siliconoxide has a thickness of about ≦5 Å.
 3. The semiconductor device ofclaim 2, wherein the complementary dielectric layer has a dielectricconstant greater than about the dielectric constant of the layer ofsilicon oxide.
 4. The semiconductor device of claim 3, wherein thecomplementary dielectric layer comprises at least one of an aluminate,silicate, ZrO₂, HfO₂, TiO₂, Gd₂O₃, Y₂O₃, Si₃N₄, Ta₂O₅ and Al₂O₃.
 5. Asemiconductor device comprising: a layer of silicon oxide, SiO_(X≦2),formed upon a semiconductor substrate, the layer of silicon oxide havinga dielectric constant greater than about 3.9 and about ≦12; and acomplementary dielectric layer disposed upon the layer of silicon oxide.6. The semiconductor device of claim 5, wherein the layer of siliconoxide has a thickness of about ≦5 Å.
 7. The semiconductor device ofclaim 6, wherein the complementary dielectric layer has a dielectricconstant greater than about the dielectric constant of the layer ofsilicon oxide.
 8. The semiconductor device of claim 7, wherein thecomplementary dielectric layer comprises at least one of an aluminate,silicate, ZrO₂, HfO₂, TiO₂, Gd₂O₃, Y₂O₃, Si₃N₄, Ta₂O₅ and Al₂O₃.
 9. Amethod of fabricating a composite gate dielectric layer comprising thestep of: forming a complementary dielectric layer upon a layer ofsilicon oxide, SiO_(X≦2), the layer of silicon oxide having a thicknessof about ≦5 Å and a dielectric constant greater than about 3.9 and about≦12.
 10. The method of claim 9, wherein step of forming a complementarydielectric layer upon a layer of silicon oxide comprises the steps of:forming a first monolayer of oxygen upon a silicon substrate by at leastone of atomic layer chemical vapor deposition, metal organic chemicalvapor deposition and low pressure chemical vapor deposition; forming amonolayer of silicon upon the first monolayer of oxygen by at least oneof atomic layer chemical vapor deposition, metal organic chemical vapordeposition and low pressure chemical vapor deposition; forming a secondmonolayer of oxygen upon the monolayer of silicon by at least one ofatomic layer chemical vapor deposition, metal organic chemical vapordeposition and low pressure chemical vapor deposition; and growing thecomplementary dielectric layer upon the second monolayer of oxygen. 11.The method of claim 10, wherein the complementary dielectric layer isgrown by at least one of metal organic chemical vapor deposition and lowpressure chemical vapor deposition.
 12. The method of claim 9 whereinthe step of forming a complementary dielectric layer upon a layer ofsilicon oxide comprises the steps of: growing a layer of silicon dioxideupon a silicon substrate; implanting a transition metal into the layerof silicon dioxide; and annealing the implanted silicon dioxide layer toform the layer of silicon oxide and the complementary dielectric layer.13. The method of claim 12, wherein the transition metal comprises atleast one of Zr, Hf and Ti.
 14. The method of claim 9, wherein the stepof forming a complementary dielectric layer upon a layer of siliconoxide comprises the steps of: forming a metal-silicide upon a siliconsubstrate; and annealing the metal-silicide to form the layer of siliconoxide upon the silicon substrate and the complementary dielectric layerupon the layer of silicon oxide.
 15. The method of claim 14, wherein thestep of forming a metal-silicide upon a silicon substrate comprises thestep of heating a silicide to release metal atoms into an O₂ atmosphere.16. The method of claim 14, wherein the step of annealing is performedin an O₂ atmosphere at a temperature of about 800° C. for a time of lessthan about 5 seconds.
 17. The method of claim 14, wherein the step offorming a metal-silicide upon a silicon substrate comprises the step ofat least one of sputtering metal atoms in an O₂ atmosphere, evaporatingmetal atoms in an O₂ atmosphere, and chemical vapor depositing metalatoms in an O₂ atmosphere.